| 1. | Description of the reliability test structures of the european mini test chip
欧洲微型试验芯片可靠性试验结构的描述 |
| 2. | Design and simulation of on - line test structure for thermal conductivity of polysilicon thin films
在线检测多晶硅薄膜热导率测试结构的设计与模拟 |
| 3. | Jx5 microprocessor ’ s testing structure comprises built - in self - test ( bist ) , boundary scan and internal scan
Jx5微处理器的测试结构由bist 、边界扫描和内部扫描三部分组成。 |
| 4. | Finally the author constructs the full testing structure of jx5 microprocessor and implements it independently
作者还独立地具体实现了这一测试方案,构造了完整的jx5的调测试结构。 |
| 5. | When a series of different levels of sine excitation force is imposedon a non - linear testing structure , the response data vary with the force
非线性系统在不同力幅的正弦激励时，其频率响应函数将随力幅而变化。 |
| 6. | Standard guide for design of flat , straight - line test structures for detecting metallization open - circuit or resistance - increase failure due to electromigration metric
检测由电迁移造成的喷镀金属开路或阻力增加失效率用的平板直线试验结构设计的标准指南 |
| 7. | Through all these work , a practical method for designing test structure , setting up automatic measurement system , collecting test data , and dealing with statistical data was given
对于导电胶可靠性的评估，从试验样品设计、自动测量系统和测量方法直到可靠性试验数据的处理和统计分析，提供了一套切实可行的方法。 |
| 8. | We have demonstrated that the integrated circuit test structures fabricated at standard commercial foundries can be radiation tolerant at total does greater than 100krad ( si ) . the radiation environment of outer space is capable of effecting cmos devices in three ways
外太空辐射环境主要以三种方式影响cmos器件：总剂量辐射效应( tid ) ，单粒子翻转效应( seu )和单粒子闩锁效应( sel ) 。 |
| 9. | Abstract : metal aluminium film em failure mechanism has been studied under pulsed stress , and the metal aluminium em reliability under pure ac stress has been discussed , a detailed spec - ification has been made about relative factor affecting test structures
摘要：对脉冲应力作用下金属铝膜的电迁移失效机理进行了研究，研究了纯交流应力对金属铝膜电迁移可靠性的影响，对影响测试结构的相关因素作了详细的描述。 |
| 10. | In this study , the design procedures for mitigating radiation effects mechanisms have been implemented in a gate array design , we have obtained samples of integrated circuits test structures manufactured by wuxi csmc - hj using their 0 . 6 - m cmos process
在研究中，我们将降低辐射效应的设计方法应用到门阵列设计中，获得了华晶上华半导体有限公司采用0 . 6 m的cmos工艺生产的集成电路样片，具有100krad ( si )的抗总剂量辐射能力。 |
